Imec reports progress in deep sub-micron scaling for logic and memory

At the International Electron Devices Meeting in San Francisco Imec's advanced CMOS research program reports promising advances in scaling logic, DRAM and non-volatile memory.

A new device based on non-silicon channels was realized to scale high-performance logic towards the sub-20nm node. Moreover,Imecdeveloped low-leakage capacitors allowingDRAMto be pushed to the 2x nm node. And the switching mechanism of resistive RAM for next-generation flash memories (RRAM) has been unraveled.

Implant-free SiGe channels to scale logic ICs towards the sub-20nm node

Further scaling of CMOS towards the sub-20nm node requires higher mobility channels and novel device structures to boost transistor performance. Imec developed a new implant-free SiGe (silicon germanium) quantum well pFET device featuring a high-mobility SiGe channel with raised SiGe source/drains using bulk-Si substrates. This high-electron mobility transistor with an EOT (effective oxide thickness) of 0.85 achieves a 50% higher saturation drive current compared to Si-controlled pFETs. The device concept is compatible with additional strain boosters paving the way to deep-submicron scaling achieving high performance.

Low-leakage MIM (metal insulator metal) capacitors enabling 2x nm node DRAM

Imec reports as the world first a viable path to scale DRAM to the 2x node by using novel stack engineering. To scale DRAM to the 2x nm node, low leakage at an EOT of 0.4nm and less is required, deposited with highly conformalatomic layer deposition(ALD) processes for compatibility with large aspect ratio structures. Up to now, this was indicated in red as“manufacturable solutions not known” by the international roadmap for semiconductors (ITRS). Imec today reports record low-leakage MIM capacitors, JG of 10^-6A/cm²at 0.4nm EOT, enabling to scale DRAM to the 2x nm node. The capacitors were realized using a novel TiN/RuOx/TiOx/STO/TiN stack fabricated in a 300mm line with DRAM compatible processes.

Fundamental understanding of switching mechanism of RRAM

RRAM is a promising alternative concept for future flash memory, indicated on the roadmap to be in production within 3 to 4 years. To realize a RRAM technology ready for mass production, fundamental understanding of the switching mechanism is required. The operation of RRAM relies on the voltage-controlled resistance change of a MIMcapacitor. Many stacks of combinations of materials need a forming step to create a small conductive filament connecting the electrodes. In the reliability community, this is known as dielectric breakdown. RRAM operation is thus based on the repetitive opening and closing of a dielectric breakdown path. Imec applied its reliability knowledge of logic to RRAM, resulting in fundamental understanding of the switching mechanism of RRAM. By finding synergies between conventional logic ICs and RRAM, imec succeeded in setting out the theory for predicting the maximum applicable Vset and revealed that the reset operation corresponds to a pinch off of the filament at its narrowest point.

These results were obtained in cooperation with Imec’s key partners in its core CMOS programs: Intel, Micron, Panasonic, Samsung, TSMC, Sony, Fujitsu, Infineon, Qualcomm, ST Microelectronic and Amkor.

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Fujitsu develops GaN HEMT power amplifier featuring world's highest output in millimeter-wave W-Band

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Fujitsu announced the development of a power amplifier using gallium nitride (GaN) High Electron Mobility Transistors (HEMT) that has achieved the world's highest output performance of 1.3W for wireless communications in the millimeter-wave W-band, for which widespread usage is expected in the future. The new amplifier will offer transmission output equivalent to approximately 16 times that of existing amplifiers that use gallium-arsenide (GaAs), thereby enabling W-band transmission ranges to be extended by approximately six times.

Fujitsu's new GaN HEMT-basedpower amplifierwill make high-capacity wireless communications possible in regions in which it is unfeasible to lay optical fiber cables, in addition to ensuring high-quality communications in rain and under other conditions where the millimeter-wave signal is known to attenuate.

Part of this research was conducted under contract as part of the Research and Development Project for Expansion ofRadio SpectrumResources of Japan's Ministry of Internal Affairs and Communications. Details of the technology will be presented at the 2010 IEEE Compound Semiconductor IC Symposium (CSICS), to be held in Monterey, California from October 3-6, 2010.

In order to accommodate the demands for greater bandwidth resulting from increases in internet communications and expansions inmobile phone networks, optic fiber cables are being laid in nations throughout the world to create a high-capacity trunk-line system. This is problematic in areas with challenging topography, which has sparked interest in high-bandwidth wireless trunk lines that are capable of data transmission capacities in the range of up to 10 Gbps-on par with optical fiber cabling-as a way to bridge the"digital divide".

The millimeter-wave W-band is an effective band for use in wireless communications at a speed up to 10 Gbps, as it is readily available. Diagram 1 shows an example of a wireless transceiver that employs the millimeter-wave W-band. The power amplifier, located inside the transmission unit, is the key component for amplifying the millimeter-wave signal to the intensity required for transmission.

Up until now, Fujitsu and Fujitsu Laboratories have succeeded in producing 350 mW of power using power amplifiers that employ GaN HEMTs. The millimeter-wave W-band, however, experiences significant signal attenuation due to factors such as atmospheric absorption and rain, and there has been demand for high-output power amplifiers that can transmit a stable signal across distances ranging from a few kilometers to several tens of kilometers.

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Cross-section diagram of millimeter-wave GaN HEMT transistor

In order to develop a millimeter-wave W-band power amplifier featuring high output, the following issues needed to be addressed.

1. Transistor operating speed, or operating frequency, is determined by the speed at which electrons in the current pass directly beneath the gate electrodes. In order to operate a transistor at a high frequency, such as the millimeter-wave band, it is necessary to decrease the length of the gate electrodes. On the other hand, an effective method of achieving high power output is by applying high voltage to the transistor. When the GaNHEMTgate length is reduced and the transistor is operated at a high voltage, however, electrons dramatically increase in speed, and as a result, a portion of the electrons can leak from the current pathway (electron channel layer), reaching as far as the passivation layer, where they will accumulate. As a result, there is a reduction in the electrons contributing to high-frequency operation, or a loss in high-frequency current, thereby making it difficult to increase power output.

2. Power distribution within a power amplifier is performed by dividing the input signal among multiple parallel transistors in the power splitter circuit. After the signal is amplified by each transistor, it is combined again using the combiner circuit, thereby enabling high-power output. At frequencies above 70 GHz, however, due to the interference of high-frequency complex signal distribution, the signal undergoes attenuation in the power splitter and combiner circuits, preventing the achievement of the desired power output. As a result, it was necessary to construct a power splitting and combination model for use in the millimeter-wave band, and develop a design that takes the complex signal distribution into consideration while enabling the desired output to be achieved.

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Structure of millimeter-wave W-band amplifier

Fujitsu developed the following technologies in order to resolve the aforementioned issues.

(1) Optimizing the GaN HEMT passivation layer
After analyzing the reason why electrons escaped from the electron channel layer and accumulated in the passivation layer, Fujitsu traced the issue to the existence of defects in the crystallization of the SiN used as part of the passivation layer. By enhancing the layer's SiN composition and crystalline structure, Fujitsu was able to build a passivation layer with minimal crystalline defects, making it difficult for electrons to accumulate. As a result, the technology was successful in amplifying high-frequency current to over two times the power of existing technology.

(2) Building a power division and combination model through electromagnetic analysis
By performing electromagnetic analysis on the complex signal distribution of the high-frequency signal, based on the physical properties of the power splitter and combiner circuits, Fujitsu successfully designed a highly precise circuit that reduces signal attenuation in the two circuits. As a result, Fujitsu was able to increase design precision by roughly 15%.

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Comparison with other millimeter-wave W-band amplifiers

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Newly developed GaN HEMT amplifier's characteristics

The above technologies were employed to develop a power amplifier for use in millimeter-wave W-band wireless equipment. The newly developed amplifier achieves a maximum output of 1.3W, which, among GaN HEMT power amplifiers, represents the world's highest output in this frequency band using single integrated circuit.

Furthermore, the new technology achieves a transmission output equivalent to 16 times that of existing amplifiers that use GaAs. When employed in combination with the GaN HEMT receiver amplifier developed by Fujitsu last year, it is expected that transmission ranges will be able to be extended by approximately six times in comparison to transceivers that employ GaAs. This will enable millimeter-wave band wireless communications equipment to be deployed in a wider range of fields, while at the same time ensuring high-quality communications in which ample signal output can be obtained even when there is signal attenuation due to rain and other factors.

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Micron unveils innovative flash memory devices that extend the life of NAND

Micron Technology, Inc. today introduced a portfolio of high-capacity flash memory products that will lengthen the life of NAND for years to come. By integrating the error management techniques in the same NAND package, the new Micron ClearNAND devices alleviate the challenges traditionally found in NAND process shrinks. Micron's ClearNAND portfolio extends the opportunities for more advanced NAND process generations to be used in enterprise servers, tablet PCs, portable media players, and dozens of other consumer applications.

"The pace of NAND scaling is largely responsible for the incredible growth and success the industry has seen to date, and for helping to create new flash-based storage solutions,"said Glen Hawk, vice president of Micron's NAND Solutions Group."While the advantages in NAND scaling are evident, so are the challenges with the technology becoming increasingly more difficult to manage. Micron's ClearNAND products remove this management burden for our customers and extend the life of this all-important technology."

Micron's ClearNAND products utilize a traditional raw NAND interface, and include new features that are optimized for high-capacity and high-performance applications. As the industry progresses past 20-nanometer (nm), flash management gets more challenging because the amount of bit errors increases dramatically, impacting NAND performance and reliability. By tightly coupling the error management with the NAND devices in a single package, Micron's customers can continue to take advantage of the highest capacity and lowest cost-per-bitflash memorysolution. Micron's ClearNAND products are first designed using its 25nm multi-level cell (MLC) process, and are available in two versions: Standard and Enhanced.

Micron's Standard ClearNAND products come in 8 to 32gigabyte(GB) packages, and are intended to remove the error correction code (ECC) burden from the host processor with minimal protocol changes compared to raw NAND. The Standard ClearNAND portfolio is targeted for portable media players and other consumer electronic devices.

Micron's Enhanced ClearNAND products, in addition to removing the ECC burden from the host processor, also provide new enterprise specific features to enable high-capacity designs, delivering improved performance and reliability. Capacities are available in 16 to 64GB packages. The Enhanced ClearNAND products are targeted at enterprise and computing applications, and allows leading-edge 25nm MLCNANDto be used in these applications for the first time.

Both Micron Standard ClearNAND and Enhanced ClearNAND products are available now.

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UCLA receives DARPA grant to research ultra-low-power, non-volatile logic technologies

The Defense Advanced Research Projects Agency (DARPA) has awarded the UCLA Henry Samueli School of Engineering and Applied Science an $8.4 million grant for research on a technology known as non-volatile logic, which enables computers and electronic devices to keep their state even while powered off, then start up and run complex programs instantaneously.

The research has broad implications across a range of technologies, includingportable electronics, remote sensors, unmanned aerial vehicles and high-performance computing.

UCLA Engineering researchers will conduct studies into the materials, design, fabrication and tools used to develop such technologies.

"The technologies developed in this project will form the basis for a paradigm shift, not only in spintronics, but in the electronics industry as a whole,"said Kang Wang, UCLA's Raytheon Professor of Electrical Engineering and joint principal investigator on the project."The support from DARPA is critical, since it will allow the U.S. to take the lead in developing this new non-volatile electronic technology."

Today's digital electronics rely on complimentary metal-oxide semiconductor (CMOS)integrated circuits, which use an electron's charge to store and transfer information. But as devices and chips have become smaller and more compact, down to thenanometer scale, the fundamental limits of CMOS are being approached. The emerging field of spintronics exploits another aspect of electrons— their spin— to transfer information, taking advantage of ferromagnetic materials, which are inherently magnetic.

Devices using ferromagnetic materials can be non-volatile, maintaining their computational state even when power is removed, and they consume much less power when switched on.

The UCLA researchers are aiming to develop a prototype non-volatile logic circuit, which could lead to the development of new classes of ultra–low-power, high-performance electronics. The research program will explore three technical areas: the behavior of nanoscale magnetic materials; the fabrication and testing of a non-volatile logic circuit; and the development of novel circuits and circuit-design tools.

Researchers at the Western Institute of Nanoelectronics (WIN) and the Center for Functional Engineered Nano-Architectronics (FENA), both housed at UCLA Engineering and both led by Wang, have made several research breakthroughs inspintronicsmaterials and design over the past several years. This research will be leveraged into the DARPA-funded non-volatile logic program.

"To achieve the ambitious goals of this program, we are planning to introduce key innovations in terms of both material and device structures. This is an opportunity to study new nano-magnetic physics while developing an exciting technology,"said research associate Pedram Khalili, who will be the project manager at UCLA.

The project will be led by UCLA under principal investigators Kang Wang and Alex Khitun, an assistant research engineer, and will involve researchers from UCLA, UC Irvine, Yale University and the University of Massachusetts.

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Samsung develops industry’s highest density LPDDR2 DRAM using 30nm-class technology

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Samsung Electronics announced today that it has developed and started sampling the industry’s first monolithic four gigabit (Gb), low power double-data-rate 2 (LPDDR2) DRAM using 30 nanometer (nm) class technology in November. The chip will be used in high-end mobile applications such as smartphones and tablet PCs.

“The mobile device market is gaining momentum with the advent of tablet PCs, which is adding significantly to the already surging smartphone segment,” said Jun-Young Jeon, vice president, memory product planning team,Samsung Electronics.“Samsung will work closely with mobile device designers to bring high-performance, high-density mobile solutions to market as rapidly as possible.”

The new 4Gb LPDDR2 DRAM can transfer up to 1,066 megabits per second (Mbps), which approaches the performance of memory solutions for PC applications. It more than doubles the performance of the industry's previous mobile DRAM— MDDR, which operates between 333Mbps and 400Mbps.

To accommodate continually diversifying consumer needs for mobile application features, advanced memory chips offering both high performance and high density are becoming essential.

Starting this month, Samsung will begin sampling 8Gb LPDDR2 DRAM by stacking two 4Gb chips in a single package, as it is expected that 8Gb will become the mainstream density for the mobile DRAM market next year.

Until now, an 8Gb (1GB) LPDDR2 DRAM used four 2Gb chips. With the new Green 4Gb LPDDR2, the 8Gb solution offers a 20 percent package height reduction (0.8mm vs. 1.0mm) and will save 25 percent of the power consumed by the previous 8Gb package that used four 2Gb chips. This enables thinner, lighter mobile devices with longer battery life.

Samsung developed a 2Gb LPDDR2 DRAMchipbased on 40nm-class technology in February of this year and has been providing that solution since April to cope with the rising demand for advanced mobile DRAMs. With the new 30nm-class 4Gb chip, Samsung will meet the sharply increasing needs for high-density LPDDR2 solutions, as the smartphone and tablet PC markets expand throughout 2011. It also plans to provide 16Gb (2GB) LPDDR2 DRAM by stacking four of the 4Gb chips, as capacity needs continue to grow.

According to iSuppli, shipments of mid to high-end smartphones will increase at about an 18 percent annual rate from 2009 to 2014. This signals dramatic expansion of the mobile DRAM market overall, which may register as much as 64 percent growth in mobile DRAM use during the same period, iSuppli also reported.

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IBM's breakthrough chip technology lights the path to exascale computing

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(PhysOrg.com) -- IBM scientists today unveiled a new chip technology that integrates electrical and optical devices on the same piece of silicon, enabling computer chips to communicate using pulses of light (instead of electrical signals), resulting in smaller, faster and more power-efficient chips than is possible with conventional technologies.

The new technology, called CMOS IntegratedSiliconNanophotonics, is the result of a decade of development at IBM's global Research laboratories. The patented technology will change and improve the waycomputer chipscommunicate– by integrating optical devices and functions directly onto a silicon chip, enabling over 10X improvement in integration density than is feasible with current manufacturing techniques.

IBM anticipates that Silicon Nanophotonics will dramatically increase the speed and performance between chips, and further the company's ambitious Exascale computing program, which is aimed at developing a supercomputer that can perform one million trillion calculations—or an Exaflop—in a single second. An Exascale supercomputer will be approximately one thousand times faster than the fastest machine today.

“The development of the Silicon Nanophotonics technology brings the vision of on-chip optical interconnections much closer to reality,” said Dr. T.C. Chen, vice president, Science and Technology, IBM Research.“Withoptical communicationsembedded into the processor chips, the prospect of building power-efficient computer systems with performance at the Exaflop level is one step closer to reality.”

In addition to combining electrical andoptical deviceson a single chip, the new IBM technology can be produced on the front-end of a standard CMOS manufacturing line and requires no new or special tooling. With this approach, silicon transistors can share the same silicon layer with silicon nanophotonics devices. To make this approach possible, IBM researchers have developed a suite of integrated ultra-compact active and passive silicon nanophotonics devices that are all scaled down to the diffraction limit– the smallest size that dielectric optics can afford.

“Our CMOS Integrated Nanophotonics breakthrough promises unprecedented increases in silicon chip function and performance via ubiquitous low-power optical communications between racks, modules, chips or even within a single chip itself,” said Dr. Yurii A. Vlasov, Manager of the Silicon Nanophotonics Department at IBM Research.“The next step in this advancement is to establishing manufacturability of this process in a commercial foundry using IBM deeply scaled CMOS processes.”

By adding just a few more processing modules to a standard CMOS fabrication flow, the technology enables a variety of siliconnanophotonicscomponents, such as: modulators, germanium photodetectors and ultra-compact wavelength-division multiplexers to be integrated with high-performance analog and digital CMOS circuitry. As a result, single-chip optical communications transceivers can now be manufactured in a standard CMOS foundry, rather than assembled from multiple parts made with expensive compound semiconductor technology.

The density of optical and electrical integration demonstrated by IBM's new technology is unprecedented– a single transceiver channel with all accompanying optical and electrical circuitry occupies only 0.5mm²– 10 times smaller than previously announced by others. The technology is amenable for building single-chip transceivers with area as small as 4x4mm²that can receive and transmit over Terabits per second that is over a trillion bits per second.

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Project pioneers use of silicon-germanium for space electronics applications

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A five-year project led by the Georgia Institute of Technology has developed a novel approach to space electronics that could change how space vehicles and instruments are designed. The new capabilities are based on silicon-germanium (SiGe) technology, which can produce electronics that are highly resistant to both wide temperature variations and space radiation.

Titled"SiGe Integrated Electronics for Extreme Environments,"the $12 million, 63-month project was funded by the National Aeronautics and Space Administration (NASA). In addition to Georgia Tech, the 11-member team included academic researchers from the University of Arkansas, Auburn University, University of Maryland, University of Tennessee and Vanderbilt University. Also involved in the project were BAE Systems, Boeing Co., IBM Corp., Lynguent Inc. and NASA's Jet Propulsion Laboratory.

"The team's overall task was to develop an end-to-end solution for NASA– a tested infrastructure that includes everything needed to design and build extreme-environment electronics for space missions,"said John Cressler, who is a Ken Byers Professor in Georgia Tech's School of Electrical and Computer Engineering. Cressler served as principal investigator and overall team leader for the project.

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A five-year project led by the Georgia Institute of Technology has developed a novel approach to space electronics that could change how space vehicles and instruments are designed. The new capabilities are based on silicon-germanium (SiGe) technology, which can produce electronics that are highly resistant to both wide temperature variations and space radiation. Credit: Georgia Tech/Inertia Films with NASA video/still images

A paper on the project findings will appear in December inIEEE Transactions on Device and Materials Reliability,2010. During the past five years, work done under the project has resulted in some 125 peer-reviewed publications.

Unique Capabilities

SiGe alloys combinesilicon, the most common microchip material, with germanium at nanoscale dimensions. The result is a robust material that offers important gains in toughness, speed and flexibility.

That robustness is crucial to silicon-germanium's ability to function in space without bulky radiation shields or large, power-hungry temperature control devices. Compared to conventional approaches, SiGe electronics can provide major reductions in weight, size, complexity, power and cost, as well as increased reliability and adaptability.

"Our team used a mature silicon-germanium technology– IBM's 0.5 micron SiGe technology– that was not intended to withstand deep-space conditions,"Cressler said."Without changing the composition of the underlying silicon-germanium transistors, we leveraged SiGe's natural merits to develop new circuit designs– as well as new approaches to packaging the final circuits– to produce an electronic system that could reliably withstand the extreme conditions of space."

At the end of the project, the researchers supplied NASA with a suite of modeling tools, circuit designs, packaging technologies and system/subsystem designs, along with guidelines for qualifying those parts for use in space. In addition, the team furnished NASA with a functional prototype– called a silicon-germanium remote electronics unit (REU) 16-channel general purpose sensor interface. The device was fabricated using silicon-germanium microchips and has been tested successfully in simulated space environments.

A New Paradigm

Andrew S. Keys, center chief technologist at the Marshall Space Flight Center and NASA program manager, said the now-completed project has moved the task of understanding and modeling silicon-germanium technology to a point where NASA engineers can start using it on actual vehicle designs.

"The silicon-germanium extreme environments team was very successful in doing what it set out to do,"Keys said."They advanced the state-of-the-art in analog silicon-germanium technology for space use– a crucial step in developing a new paradigm leading to lighter weight and more capable space vehicle designs."

Keys explained that, at best, most electronics conform to military specifications, meaning they function across a temperature range of minus- 55 degrees Celsius to plus-125 degrees Celsius. But electronics in deep space are typically exposed to far greater temperature ranges, as well as to damaging radiation. The Moon's surface cycles between plus-120 Celsius during the lunar day to minus-180 Celsius at night.

The silicon-germanium electronics developed by the extreme environments team has been shown to function reliably throughout that entire plus-120 to minus-180 Celsius range. It is also highly resistant or immune to various types of radiation.

The conventional approach to protecting space electronics, developed in the 1960s, involves bulky metal boxes that shield devices from radiation and temperature extremes, Keys explained. Designers must place most electronics in a protected, temperature controlled central location and then connect them via long and heavy cables to sensors or other external devices.

By eliminating the need for most shielding and special cables, silicon-germanium technology helps reduce the single biggest problem in space launches– weight. Moreover, robust SiGe circuits can be placed wherever designers want, which helps eliminate data errors caused by impedance variations in lengthy wiring schemes.

"For instance, the Mars Exploration Rovers, which are no bigger than a golf cart, use several kilometers of cable that lead into a warm box,"Keys said."If we can move most of those electronics out to where the sensors are on the robot's extremities, that will reduce cabling, weight, complexity and energy use significantly."

A Collaborative Effort

NASA currently rates the new SiGe electronics at a technology readiness level of six, which means the circuits have been integrated into a subsystem and tested in a relevant environment. The next step, level seven, involves integrating the SiGe circuits into a vehicle for space flight testing. At level eight, a new technology is mature enough to be integrated into a full mission vehicle, and at level nine the technology is used by missions on a regular basis.

Successful collaboration was an important part of the silicon-germanium team's effectiveness, Keys said. He remarked that he had"never seen such a diverse team work together so well."

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This close-up image shows a remote electronics unit 16-channel sensor interface, developed for NASA using silicon-germanium microchips by an 11-member team led by Georgia Tech. Credit: Credit: Gary Meek

Professor Alan Mantooth, who led a large University of Arkansas contingent involved in modeling and circuit-design tasks, agreed. He called the project"the most successful collaboration that I've been a part of."

Mantooth termed the extreme-electronics project highly useful in the education mission of the participating universities. He noted that a total of 82 students from six universities worked on the project over five years.

Richard W. Berger, a BAE Systems senior systems architect who collaborated on the project, also praised the student contributions.

"To be working both in analog and digital, miniaturizing, and developing extreme-temperature and radiation tolerance all at the same time– that's not what you'd call the average student design project,"Berger said.

Miniaturizing an Architecture

BAE Systems' contribution to the project included providing the basic architecture for the remote electronics unit (REU) sensor interface prototype developed by the team. That architecture came from a previous electronics generation: the now cancelled Lockheed Martin X-33 Spaceplane initially designed in the 1990s.

In the original X-33 design, Berger explained, each sensor interface used an assortment of sizeable analog parts for the front end signal receiving section. That section was supported by a digital microprocessor, memory chips and an optical bus interface– all housed in a protective five-pound box.

Theextreme environmentsteam transformed the bulky X-33 design into a miniaturized sensor interface, utilizing silicongermanium. The resulting SiGe device weighs about 200 grams and requires no temperature or radiation shielding. Large numbers of these robust, lightweight REU units could be mounted on spacecraft or data-gathering devices close to sensors, reducing size, weight, power and reliability issues.

Berger said that BAE Systems is interested in manufacturing a sensor interface device based on the extreme environment team's discoveries.

Other space-oriented companies are also pursuing the new silicon-germanium technology, Cressler said. NASA, he explained, wants the intellectual-property barriers to the technology to be low so that it can be used widely.

"The idea is to make this infrastructure available to all interested parties,"he said."That way it could be used for any electronics assembly– an instrument, a spacecraft, an orbital platform, lunar-surface applications, Titan missions– wherever it can be helpful. In fact, the process of defining such an NASA mission-insertion road map is currently in progress."

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