DOCOMO develops compact multi-band power amplifier

NTT DOCOMO today announced that it has developed a prototype power amplifier for six frequency bands between 1.5 GHz and 2.5 GHz in a form factor smaller than multiple single-band power amplifiers conventionally used to provide the same function.

The amplifier’s compact size and six-band versatility, which eliminates the need for sets of single-band power amplifiers, will enable other components to use space normally occupied by the single-band power amplifiers. Power amplifiers are electronic circuits that amplify input signals to levels required for communications.

Packaged on a rectangular printed circuit board measuring just 8.05 mm x 6.2 mm, DOCOMO’s new prototype meets requirements for LTE, W-CDMA and GSM mobile communication standards, making it suitable for most domestic and international networks that use frequency bands between 1.5 GHz and 2.5 GHz.

Developed by DOCOMO with the support from Renesas Electronics Corporation, the prototype is a downsized, commercially viable version of the multi-bandpower amplifierthat DOCOMO announced on January 8, 2010.

DOCOMO will exhibit the amplifier during Wireless Japan 2011 at Tokyo Big Sight from May 25 to 27, and during CommunicAsia 2011 at Marina Bay Sands, Singapore from June 21 to 24.

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Development of CMOS LSI technology for 100Gbit ethernet optical transceivers

Hitachi today announced the successful prototyping of a low-power CMOS gearbox LSI conforming with international standards, which was developed for optical transceivers as part of the effort to reduce power consumption in routers and network equipment to be used in the 100 gigabit (Gbit) Ethernet (henceforth, 100GbE). Optical receivers convert optical signals and electrical signals. The 100GbE CMOS gearbox LSI functions to convert the transmission rate and number of channels, converting the 4 channel× 25 gigabit per second (henceforth, Gb/s) electrical signals received from the network into 10 channels× 10Gb/s electrical signals which can be used within the equipment, and vice versa. Until now, a high-speed gearbox LSI based on SiGe process technology was used for this purpose, however, the achievement of a low-cost and low-power LSI based on the CMOS process was desired. The prototype 100 GbE gearbox LSI fabricated employs the four-phase clock circuit scheme using CMOS process technology, and achieves operation with a low power consumption of 2W, which is approximately one-quarter that of a SiGe gearbox LSI.

This work was partially supported by the"Universal Link"project of the National Institute of Information and Communications Technology (NICT), Japan.

Network traffic continues to dramatically increase each year with the rapid development of the broadband environment and the increasing use of high-definition video contents in this age of broadcast and communication convergence. As a result, the need exists for a communication network that provides both high speed and large capacity. In current internet communication, the Ethernet with a communication speed of 10Gb/s is widely used, however, to enable even higher speed, technology for a next generation 100GbE (10 times faster than the current level) was internationally standardized in June 2010. Today, technology development to conform with this standard is being conducted worldwide however a major issue of how to reduce the increasing power consumption which grows proportionally with increasing speed, remained.

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Against this backdrop, Hitachi developed a prototype low-power CMOS gearbox LSI for optical transceivers used in routers and network equipment conforming with the 100GbE international standards. The technology developed includes the"four-phase clock circuit"which maintains the data processing speed of the LSI while reducing the circuit operating speed by 75％, and implementing this in the 25Gb/s interface circuit of the CMOS gearbox LSI. In addition, the CMOS interface (SerDes) circuit developed in 2010 byHitachiwhich has a low power consumption characteristic of 0.98mW per 1Gb/s, was employed in the prototype CMOS gearbox LSI.

Verification tests confirmed that the developed CMOS gearbox LSI operated with a power consumption of 2W; namely, a quarter that of a conventional SiGe gearbox LSI. The CMOS gearbox LSI developed can be applied to not only the 100GbE applications but also in signal transmission between LSIs in information-processing equipment such as servers androuters, and is expected to widely contribute to low power consumption of information-processing equipment.

These results will be presented at the International Solid-StateCircuitsConference (ISSCC 2011), to be held from 20th to 24th February 2011 in San Francisco, U.S.

Details of circuit scheme developed
A four-phase-clock circuit scheme to realize lowpower consumption

In the receiving circuit of the 25Gb/s interface circuit, a circuit scheme that determines the level and phase of the received data by using four (phase) clocks with phase differences of 90 degrees, was applied. Through this approach, the interface is operated at a clock rate of 6.25GHz (a quarter of the bit rate) while maintaining the data-processing speed of the LSI, and power consumption is also reduced.

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In addition, in a conventional receiving circuit, a receiving clock signal is generated by, first, distributing a high-speed 12.5GHz clock from a common PLL to four channels in the 25Gb/s interface circuit and then uses a phase-control circuit; a process consuming a large amount of power. A four-phase clock reducing thispower consumptionwas achieved by placing a PLL in each channel of the receiving circuit, dispensing with the need for a power-hungry phase-control circuit. Further power conservation was achieved through this new circuit scheme by controlling the clock frequency allocated to each channel to a low-speed of 625MHz.

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Samsung offers industry's first 64-gigabit MLC NAND flash, using toggle DDR 2.0 interface

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Samsung Electronics today announced that it has started the industry's first production of a high-performance toggle DDR 2.0 multi-level-cell (MLC) memory chip. The new NAND flash chip features a 64 gigabit (Gb) density, made possible by using an advanced 20 nanometer (nm) class process technology. The chip is designed to support the high-performance requirements of mobile devices such as smartphones, tablets and solid state drives (SSDs).

Equipped with a toggle DDR (Double Data Rate) 2.0 interface, the new 64Gb MLC chip can transmit data at a bandwidth of up to 400 megabit per second (Mbps). This provides a 10-fold increase over the 40Mbps Single Data Rate (SDR) NAND flash memory in widespread use today, and a three-fold boost over 133Mbps toggle DDR 1.0, 32Gb NAND flash memory, which Samsung was first to produce in 2009.

“With this 20nm-class, 64Gb, toggle DDR 2.0 NAND, Samsung is leading the market, which is evolving to fourth-generation smartphones and SATA 6Gbps SSDs,” said Wanhoon Hong, executive vice president, memory sales&marketing,Samsung Electronics.“We will continue to aggressively develop the world's most advanced toggle DDR NAND flash solutions with higher performance and density, since we see them as vital to enabling a greater diversity of services for mobile phone users worldwide.”

The high-speed 400Mbps bandwidth of toggle DDR 2.0 is expected to better support the ongoing shift toward advanced interfaces, as more mobile and consumer electronics devices requiring added performance and higher densities adopt new interfaces such as USB 3.0 and SATA 6.0Gbps,

Further, the new 64Gb MLC NAND chip offers an approximate 50-percent increase in productivity over 20nm-class 32Gb MLC NAND chips with a toggle DDR 1.0 interface (which Samsung started producing in April last year) and more than doubles the productivity of 30nm-class 32Gb MLC NAND.

According to IHS iSuppli, the worldwide NAND flash memory market will continue to steadily grow from approximately 11 billion 1 Gigabyte (GB) equivalent unitsin 2010 to 94 billion 1GB equivalent units in 2015 with a CAGR of 54 percent. In addition, shipments of NANDflash memorywith 64Gb or higher density are expected to account for approximately 70 percent of totalNAND flashmemory shipments in 2012, a huge increase from the three percent level in 2010.

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Toshiba develops 7.0-inch LTPS TFT LCD panel

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Toshiba Mobile Display has developed a 7.0-inch low-temperature poly-silicon (LTPS) thin-film transistor (TFT) liquid crystal display (LCD) for vehicle-mounted and industrial uses that enables multi-touch input on the display screen without the need for additional installation of a touch panel as a demonstration of its new touch panel technology.

The technology enables an integrated touch panel function by forming the display pixel electrodes and TFT within the LCD panel using LTPS TFT technology and creating a detecting circuit for electrostatic capacitance changes between the electrodes and the peripheral object. Compared to conventional LCDs with an external touch panel, the thickness is reduced by 57 percent to approximately 1 millimeter, the weight is reduced by 48 percent to 225 grams and the surface reflection ratio is reduced by 10 percent. Its smaller size enables the design of more compact products for mobile applications, reduces the impact on the environment by saving resources and power, provides crisp and clear images with minimal reflection of natural light even in a bright environment, and features intuitive multi-touch input.

Recently, an increasing number of smartphones, cellular phones, in-vehicle car navigation systems, tablet-type PCs and other equipment formobile applicationshave been designed around a capacitive-type touch panel1 integrated LCD, thereby facilitating the rapid spread of products that feature a low-profile and reduced-weight design, and intuitive, easy and simple touch input. TMD has developed this technology in response to the increasing demand for in-cell touch panel2 LCDs with the touch panel function integrated in the LCD panel for further reduction of thickness, weight and environmental impact.

The capacitive-type touch panel is designed to form transparent electrodes on the touch panel and detect changes in electrostatic capacitance between theelectrodesand the user’s fingers with high accuracy, thereby enabling the screen panel to respond easily to light finger touches. To integrate this feature in the LCD panel it is essential to suppress possible interference with various signals in the LCD panel. To address the problem, TMD has developed a proprietary sensor circuit, taking advantage of LTPS TFT technology. Specifically, an amplifier circuit is formed in the pixels to amplify the signals, which are then detected by the sensor for output, providing a configuration to precisely transmit sensor signals to the outside of LCD panel. This helps achieve consistent and fast-responding touch panel operation.

This technology will be exhibited in the Toshiba booth #1119 at SID 2011 International Symposium, Seminar and Exhibition to be held from May 17 to May 19, 2011 in Los Angeles, Calif., USA.

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Elpida develops industry's first 25nm process DRAM

Elpida Memory, Japan's leading global supplier of Dynamic Random Access Memory (DRAM), today announced it had developed a 2-gigabit DDR3 SDRAM using an industry-leading 25nm process for memory manufacturing. Using the most advanced process technology available Elpida has achieved the industry's smallest chip size for a 2-gigabit SDRAM.

The newly developed 25nm DRAM process technology requires 30% less cell area per bit compared with Elpida's 30nm process. The chip output for a 2-gigabit DDR3 SDRAMwaferusing the new process is about 30% higher versus 30nm.

The new SDRAM is an eco-friendly as it contributes to lowerenergy consumptionby PCs and digital consumer electronics. It outperforms Elpida's 30nm process products by saving on electric current (15% less operating current and 20% less current when on standby).

At the time the 25nm process was developed the structural changes required to shift from a 30nm process were minimized to hold down the capital expenditure needed for ramping up 25nm volume manufacturing.

By the end of 2011 Elpida also plans to begin volume production of 4-gigabit DDR3 SDRAM products using the 25nm process. Compared with the 30nm process a 44% increase in chip output per wafer is expected for this 4-gigabit DDR3 product. In addition, the new 25nm process will be used to support further development of Mobile RAMTM, Elpida's mainstaymemoryproduct.

The 25nm process 2-gigabit DDR3 SDRAM can support ultra-fast performance above DDR3-1866 (1866Mbps) and is compliant with low-voltage 1.35V high-speed DDR3L-1600 (1600Mbps).

Both sample shipments of the new 25nm 2-gigabitDDR3 SDRAMand volume production are expected to begin in July 2011.

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Taiwanese group introduces new MorPACK, stacked chip

(PhysOrg.com) -- Taiwan's National Chip Implementation Center (CIC) has announced a new chip bundling design that they claim can cut development costs in half while also reducing the time it takes to bring a new chipset to market for a particular product, by as much as two thirds. Named the MorPACK, the chipset design uses a stacked approach, whereby newly designed chips can be stacked on top of existing processors (with air flow between them), reducing the space required to hold them, and increasing speed communication times between components as they are brought closer together.

In apaper submittedtoiMAPS, author Shih-Lun Chen, of CIC, describes the structure of the MorPACK (short for morphing package) as a“heterogeneous integrated platform” of integrated parts that are put together as sort of building blocks, which allows the chipsets to require a smaller footprint. He also notes that due to the close proximity of the chips to one another in the stacked configuration, special care had to be taken to deal with heat issues; clearly something other’s that wish to consider the chipset in their electronic devices will want to take a close look at as well.

The MorPack is built from the ground up; first, at the bottom is the processor, the biggest heat generator, which will likely sit atop a heat sink; above that are layer chips (connected by bridges) to provide linkage to memory chips, and then another to provide the same for peripheral devices. And then on top, come the custom chips designed by the companies that buy the MorPACK for use in their equipment.

Chiueh Tzi-dar, director general of the laboratory at CIC where thechipwas designed, in interviews has stated that the MorPACK could be used for virtually anydevicethat currently employs integrated chips; which of course would include all the consumer devices we’ve all grown used to; such as cell phones, cameras, etc. If this turns out to be true, all such devices could eventually be made even smaller than they are now due to the smaller footprint needed for the chipsets inside; though the current configuration of the MorPACK is 4 x 4 centimeters, project development leader Chun-ming Huang says he believes he and his team can reduce it to just a fourth that size, making it small enough to fit in devices as yet unimagined.

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Texas instruments introduces industry’s smallest wireless power receiver chip

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Texas Instruments today introduced its next generation of wireless power technology, which is 80-percent smaller than TI's previous receiver chip.

The tiny, highly integrated device makes it easy for designers to implement wireless charging in their existing and new designs for portable consumer devices, such as smart phones, gaming systems, digital cameras, and medical and industrial equipment.

The bq51013 receiver integrated circuit (IC) combines voltage conditioning and full wireless power control in a small 1.9-mm x 3-mm WCSP package. The new circuit supports up to 5 W of output power, provides up to 93-percent efficient AC/DCpower conversionand is the only IC required between the receiver coil and system.

"Smartphoneand consumer electronics manufacturers are demanding wireless power, and TI is well positioned to help our customers drive widespread adoption of this technology that makes life easier for people on the go to charge their devices,"said Sami Kiriaki, senior vice president over TI'sPower Managementbusiness."Designers can use the bq51013 to quickly integrate wireless power into existing and new applications with minimal impact to overall solution size."

Key features and benefits

• Highly integrated and efficient wireless power receiver IC includes full-bridge synchronous rectification, voltage conditioning and wireless power control in a single device.

• 1.9-mm x 3-mm WCSP package allows for easy integration with minimal size impact. Device area is 80 percent less than TI's first-generation receiver.

• The receiver and its associated bq500110 transmitter IC are Wireless Power Consortium (WPC) Qi-compliant. This compliance ensures interoperability between various charging pads and portable devices.

• Built-in protection against voltage, current and temperature fault conditions, assures safe and reliable system operation.

• 93-percent peak efficiency reduces thermal rise inside the system while allowing charge rates comparable to an AC adapter.

The bq51013 wireless power receiver is available now in a 1.9-mm x 3-mm WCSP package, priced at $3.50 in quantities of 1,000.

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World's highest performance RF digital-to-analog converter announced by NXP

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NXP Semiconductors today announced the DAC1627D– a 16-bit dual-channel LVDS DDR interface Digital-to-Analog Converter (DAC) which supports output update rates of up to 1.25 Gsps. In terms of dynamic performance specifications, this new high-speed DAC offers best-in-class single tone SFDR performance and two-tone intermodulation distortion over a broad output bandwidth of 200 MHz. The first public demonstration of the DAC1627D will be made in the NXP booth (no. 420) at IMS2011, the IEEE MTT-S International Microwave Symposium held June 7-9, 2011 in Baltimore, Maryland.

Developed primarily for wireless infrastructure applications, the DAC1627D1G25 is fully compliant to the Multi-Carrier GSM spectral mask and the LTE and LTE-Advanced transmit specification, with comfortable margins. As a result, the DAC1627D is ideal for multi-standard radio base stations, allowing design engineers to employ a single DAC transmit architecture, which minimizes the system bill-of-material costs.
 
"The technology advances in cellular infrastructure demand ever higher performance in RF data converters. The introduction of NXP's DAC1627D, its high performance and high-speed digital to analog converter device, provides a compelling solution in this quickly evolving segment,” said Flint Pulskamp, wireless and wired communications semiconductor analyst at IDC.
 
"The achievement announced today, the highest performance RF DAC, is a culmination of decades of experience and innovation in high performance data converters,” said Maury Wood, general manager, High Speed Converters product line, NXP Semiconductors.“When combined with CGVxpress™ and CGV™, NXP’s implementation of the industry-leading JESD204A high speed serial interface, NXP has a roadmap that meets the most demanding digital radio transmitter signal fidelity requirements. NXP continues to work closely with our customers to bring new levels of radio frequency digital-to-analog performance to next-generation radio base stations, and other digital communications and signal synthesis applications."
 
The DAC1627D incorporates elements of NXP's CGV technology feature set, including Multi-Device Synchronization (MDS), which solves tough system synchronization and latency challenges in many digital communications system applications, including MIMO and active antenna array LTE radio base stations.
 
At IMS2011, NXP will also showcase the DAC1627D1G25 plus the BGX7100 IQ Modulator on a dedicated evaluation/demonstration printed circuit board which, in combination, deliver optimum RF performance.

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