Saturday, May 21, 2011

DOCOMO develops compact multi-band power amplifier

DOCOMO develops compact multi-band power amplifier

NTT DOCOMO today announced that it has developed a prototype power amplifier for six frequency bands between 1.5 GHz and 2.5 GHz in a form factor smaller than multiple single-band power amplifiers conventionally used to provide the same function.

The amplifier’s compact size and six-band versatility, which eliminates the need for sets of single-band power amplifiers, will enable other components to use space normally occupied by the single-band power amplifiers. Power amplifiers are electronic circuits that amplify input signals to levels required for communications.

Packaged on a rectangular printed circuit board measuring just 8.05 mm x 6.2 mm, DOCOMO’s new prototype meets requirements for LTE, W-CDMA and GSM mobile communication standards, making it suitable for most domestic and international networks that use frequency bands between 1.5 GHz and 2.5 GHz.

Developed by DOCOMO with the support from Renesas Electronics Corporation, the prototype is a downsized, commercially viable version of the multi-bandthat DOCOMO announced on January 8, 2010.

DOCOMO will exhibit the amplifier during Wireless Japan 2011 at Tokyo Big Sight from May 25 to 27, and during CommunicAsia 2011 at Marina Bay Sands, Singapore from June 21 to 24.


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Friday, May 20, 2011

Development of CMOS LSI technology for 100Gbit ethernet optical transceivers

Development of CMOS LSI technology for 100Gbit ethernet optical transceivers

Hitachi today announced the successful prototyping of a low-power CMOS gearbox LSI conforming with international standards, which was developed for optical transceivers as part of the effort to reduce power consumption in routers and network equipment to be used in the 100 gigabit (Gbit) Ethernet (henceforth, 100GbE). Optical receivers convert optical signals and electrical signals. The 100GbE CMOS gearbox LSI functions to convert the transmission rate and number of channels, converting the 4 channel× 25 gigabit per second (henceforth, Gb/s) electrical signals received from the network into 10 channels× 10Gb/s electrical signals which can be used within the equipment, and vice versa. Until now, a high-speed gearbox LSI based on SiGe process technology was used for this purpose, however, the achievement of a low-cost and low-power LSI based on the CMOS process was desired. The prototype 100 GbE gearbox LSI fabricated employs the four-phase clock circuit scheme using CMOS process technology, and achieves operation with a low power consumption of 2W, which is approximately one-quarter that of a SiGe gearbox LSI.

This work was partially supported by the"Universal Link"project of the National Institute of Information and Communications Technology (NICT), Japan.

Network traffic continues to dramatically increase each year with the rapid development of the broadband environment and the increasing use of high-definition video contents in this age of broadcast and communication convergence. As a result, the need exists for a communication network that provides both high speed and large capacity. In current internet communication, the Ethernet with a communication speed of 10Gb/s is widely used, however, to enable even higher speed, technology for a next generation 100GbE (10 times faster than the current level) was internationally standardized in June 2010. Today, technology development to conform with this standard is being conducted worldwide however a major issue of how to reduce the increasing power consumption which grows proportionally with increasing speed, remained.

Development of CMOS LSI technology  for 100Gbit ethernet optical transceivers
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Against this backdrop, Hitachi developed a prototype low-power CMOS gearbox LSI for optical transceivers used in routers and network equipment conforming with the 100GbE international standards. The technology developed includes the"four-phase clock circuit"which maintains the data processing speed of the LSI while reducing the circuit operating speed by 75%, and implementing this in the 25Gb/s interface circuit of the CMOS gearbox LSI. In addition, the CMOS interface (SerDes) circuit developed in 2010 bywhich has a low power consumption characteristic of 0.98mW per 1Gb/s, was employed in the prototype CMOS gearbox LSI.

Verification tests confirmed that the developed CMOS gearbox LSI operated with a power consumption of 2W; namely, a quarter that of a conventional SiGe gearbox LSI. The CMOS gearbox LSI developed can be applied to not only the 100GbE applications but also in signal transmission between LSIs in information-processing equipment such as servers and, and is expected to widely contribute to low power consumption of information-processing equipment.

These results will be presented at the International Solid-StateConference (ISSCC 2011), to be held from 20th to 24th February 2011 in San Francisco, U.S.

Details of circuit scheme developed
A four-phase-clock circuit scheme to realize lowpower consumption

In the receiving circuit of the 25Gb/s interface circuit, a circuit scheme that determines the level and phase of the received data by using four (phase) clocks with phase differences of 90 degrees, was applied. Through this approach, the interface is operated at a clock rate of 6.25GHz (a quarter of the bit rate) while maintaining the data-processing speed of the LSI, and power consumption is also reduced.

Development of CMOS LSI technology for 100Gbit ethernet optical transceivers
Development of CMOS LSI technology for 100Gbit ethernet optical transceivers
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In addition, in a conventional receiving circuit, a receiving clock signal is generated by, first, distributing a high-speed 12.5GHz clock from a common PLL to four channels in the 25Gb/s interface circuit and then uses a phase-control circuit; a process consuming a large amount of power. A four-phase clock reducing thiswas achieved by placing a PLL in each channel of the receiving circuit, dispensing with the need for a power-hungry phase-control circuit. Further power conservation was achieved through this new circuit scheme by controlling the clock frequency allocated to each channel to a low-speed of 625MHz.


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Saturday, May 14, 2011

Samsung offers industry's first 64-gigabit MLC NAND flash, using toggle DDR 2.0 interface

Samsung offers industry’s first 64-gigabit MLC NAND flash, using toggle DDR 2.0 interface

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Samsung Electronics today announced that it has started the industry's first production of a high-performance toggle DDR 2.0 multi-level-cell (MLC) memory chip. The new NAND flash chip features a 64 gigabit (Gb) density, made possible by using an advanced 20 nanometer (nm) class process technology. The chip is designed to support the high-performance requirements of mobile devices such as smartphones, tablets and solid state drives (SSDs).

Equipped with a toggle DDR (Double Data Rate) 2.0 interface, the new 64Gb MLC chip can transmit data at a bandwidth of up to 400 megabit per second (Mbps). This provides a 10-fold increase over the 40Mbps Single Data Rate (SDR) NAND flash memory in widespread use today, and a three-fold boost over 133Mbps toggle DDR 1.0, 32Gb NAND flash memory, which Samsung was first to produce in 2009.

“With this 20nm-class, 64Gb, toggle DDR 2.0 NAND, Samsung is leading the market, which is evolving to fourth-generation smartphones and SATA 6Gbps SSDs,” said Wanhoon Hong, executive vice president, memory sales&marketing,.“We will continue to aggressively develop the world's most advanced toggle DDR NAND flash solutions with higher performance and density, since we see them as vital to enabling a greater diversity of services for mobile phone users worldwide.”

The high-speed 400Mbps bandwidth of toggle DDR 2.0 is expected to better support the ongoing shift toward advanced interfaces, as more mobile and consumer electronics devices requiring added performance and higher densities adopt new interfaces such as USB 3.0 and SATA 6.0Gbps,

Further, the new 64Gb MLC NAND chip offers an approximate 50-percent increase in productivity over 20nm-class 32Gb MLC NAND chips with a toggle DDR 1.0 interface (which Samsung started producing in April last year) and more than doubles the productivity of 30nm-class 32Gb MLC NAND.

According to IHS iSuppli, the worldwide NAND flash memory market will continue to steadily grow from approximately 11 billion 1 Gigabyte (GB) equivalent unitsin 2010 to 94 billion 1GB equivalent units in 2015 with a CAGR of 54 percent. In addition, shipments of NANDwith 64Gb or higher density are expected to account for approximately 70 percent of totalmemory shipments in 2012, a huge increase from the three percent level in 2010.


Source

Tuesday, May 10, 2011

Toshiba develops 7.0-inch LTPS TFT LCD panel

7.0-inch LTPS TFT LCD panel developed as a demonstration of its integrated in-cell touch panel technology

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Toshiba Mobile Display has developed a 7.0-inch low-temperature poly-silicon (LTPS) thin-film transistor (TFT) liquid crystal display (LCD) for vehicle-mounted and industrial uses that enables multi-touch input on the display screen without the need for additional installation of a touch panel as a demonstration of its new touch panel technology.

The technology enables an integrated touch panel function by forming the display pixel electrodes and TFT within the LCD panel using LTPS TFT technology and creating a detecting circuit for electrostatic capacitance changes between the electrodes and the peripheral object. Compared to conventional LCDs with an external touch panel, the thickness is reduced by 57 percent to approximately 1 millimeter, the weight is reduced by 48 percent to 225 grams and the surface reflection ratio is reduced by 10 percent. Its smaller size enables the design of more compact products for mobile applications, reduces the impact on the environment by saving resources and power, provides crisp and clear images with minimal reflection of natural light even in a bright environment, and features intuitive multi-touch input.

Recently, an increasing number of smartphones, cellular phones, in-vehicle car navigation systems, tablet-type PCs and other equipment forhave been designed around a capacitive-type touch panel1 integrated LCD, thereby facilitating the rapid spread of products that feature a low-profile and reduced-weight design, and intuitive, easy and simple touch input. TMD has developed this technology in response to the increasing demand for in-cell touch panel2 LCDs with the touch panel function integrated in the LCD panel for further reduction of thickness, weight and environmental impact.

The capacitive-type touch panel is designed to form transparent electrodes on the touch panel and detect changes in electrostatic capacitance between theand the user’s fingers with high accuracy, thereby enabling the screen panel to respond easily to light finger touches. To integrate this feature in the LCD panel it is essential to suppress possible interference with various signals in the LCD panel. To address the problem, TMD has developed a proprietary sensor circuit, taking advantage of LTPS TFT technology. Specifically, an amplifier circuit is formed in the pixels to amplify the signals, which are then detected by the sensor for output, providing a configuration to precisely transmit sensor signals to the outside of LCD panel. This helps achieve consistent and fast-responding touch panel operation.

This technology will be exhibited in the Toshiba booth #1119 at SID 2011 International Symposium, Seminar and Exhibition to be held from May 17 to May 19, 2011 in Los Angeles, Calif., USA.


Source

Monday, May 9, 2011

Elpida develops industry's first 25nm process DRAM

Elpida Memory, Japan's leading global supplier of Dynamic Random Access Memory (DRAM), today announced it had developed a 2-gigabit DDR3 SDRAM using an industry-leading 25nm process for memory manufacturing. Using the most advanced process technology available Elpida has achieved the industry's smallest chip size for a 2-gigabit SDRAM.

The newly developed 25nm DRAM process technology requires 30% less cell area per bit compared with Elpida's 30nm process. The chip output for a 2-gigabit DDR3 SDRAMusing the new process is about 30% higher versus 30nm.

The new SDRAM is an eco-friendly as it contributes to lowerby PCs and digital consumer electronics. It outperforms Elpida's 30nm process products by saving on electric current (15% less operating current and 20% less current when on standby).

At the time the 25nm process was developed the structural changes required to shift from a 30nm process were minimized to hold down the capital expenditure needed for ramping up 25nm volume manufacturing.

By the end of 2011 Elpida also plans to begin volume production of 4-gigabit DDR3 SDRAM products using the 25nm process. Compared with the 30nm process a 44% increase in chip output per wafer is expected for this 4-gigabit DDR3 product. In addition, the new 25nm process will be used to support further development of Mobile RAMTM, Elpida's mainstayproduct.

The 25nm process 2-gigabit DDR3 SDRAM can support ultra-fast performance above DDR3-1866 (1866Mbps) and is compliant with low-voltage 1.35V high-speed DDR3L-1600 (1600Mbps).

Both sample shipments of the new 25nm 2-gigabitand volume production are expected to begin in July 2011.


Source

Sunday, May 8, 2011

Taiwanese group introduces new MorPACK, stacked chip

(PhysOrg.com) -- Taiwan's National Chip Implementation Center (CIC) has announced a new chip bundling design that they claim can cut development costs in half while also reducing the time it takes to bring a new chipset to market for a particular product, by as much as two thirds. Named the MorPACK, the chipset design uses a stacked approach, whereby newly designed chips can be stacked on top of existing processors (with air flow between them), reducing the space required to hold them, and increasing speed communication times between components as they are brought closer together.

In apaper submittedtoiMAPS, author Shih-Lun Chen, of CIC, describes the structure of the MorPACK (short for morphing package) as a“heterogeneous integrated platform” of integrated parts that are put together as sort of building blocks, which allows the chipsets to require a smaller footprint. He also notes that due to the close proximity of the chips to one another in the stacked configuration, special care had to be taken to deal with heat issues; clearly something other’s that wish to consider the chipset in their electronic devices will want to take a close look at as well.

The MorPack is built from the ground up; first, at the bottom is the processor, the biggest heat generator, which will likely sit atop a heat sink; above that are layer chips (connected by bridges) to provide linkage to memory chips, and then another to provide the same for peripheral devices. And then on top, come the custom chips designed by the companies that buy the MorPACK for use in their equipment.

Chiueh Tzi-dar, director general of the laboratory at CIC where thewas designed, in interviews has stated that the MorPACK could be used for virtually anythat currently employs integrated chips; which of course would include all the consumer devices we’ve all grown used to; such as cell phones, cameras, etc. If this turns out to be true, all such devices could eventually be made even smaller than they are now due to the smaller footprint needed for the chipsets inside; though the current configuration of the MorPACK is 4 x 4 centimeters, project development leader Chun-ming Huang says he believes he and his team can reduce it to just a fourth that size, making it small enough to fit in devices as yet unimagined.


Source

Saturday, May 7, 2011

Texas instruments introduces industry’s smallest wireless power receiver chip

Texas instruments introduces industry’s smallest wireless power receiver chip

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Texas Instruments today introduced its next generation of wireless power technology, which is 80-percent smaller than TI's previous receiver chip.

The tiny, highly integrated device makes it easy for designers to implement wireless charging in their existing and new designs for portable consumer devices, such as smart phones, gaming systems, digital cameras, and medical and industrial equipment.

The bq51013 receiver integrated circuit (IC) combines voltage conditioning and full wireless power control in a small 1.9-mm x 3-mm WCSP package. The new circuit supports up to 5 W of output power, provides up to 93-percent efficient AC/DCand is the only IC required between the receiver coil and system.

"and consumer electronics manufacturers are demanding wireless power, and TI is well positioned to help our customers drive widespread adoption of this technology that makes life easier for people on the go to charge their devices,"said Sami Kiriaki, senior vice president over TI'sbusiness."Designers can use the bq51013 to quickly integrate wireless power into existing and new applications with minimal impact to overall solution size."

Key features and benefits

• Highly integrated and efficient wireless power receiver IC includes full-bridge synchronous rectification, voltage conditioning and wireless power control in a single device.

• 1.9-mm x 3-mm WCSP package allows for easy integration with minimal size impact. Device area is 80 percent less than TI's first-generation receiver.

• The receiver and its associated bq500110 transmitter IC are Wireless Power Consortium (WPC) Qi-compliant. This compliance ensures interoperability between various charging pads and portable devices.

• Built-in protection against voltage, current and temperature fault conditions, assures safe and reliable system operation.

• 93-percent peak efficiency reduces thermal rise inside the system while allowing charge rates comparable to an AC adapter.

The bq51013 wireless power receiver is available now in a 1.9-mm x 3-mm WCSP package, priced at $3.50 in quantities of 1,000.


Source

Friday, May 6, 2011

World's highest performance RF digital-to-analog converter announced by NXP

World's highest performance RF digital-to-analog converter

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NXP Semiconductors today announced the DAC1627D– a 16-bit dual-channel LVDS DDR interface Digital-to-Analog Converter (DAC) which supports output update rates of up to 1.25 Gsps. In terms of dynamic performance specifications, this new high-speed DAC offers best-in-class single tone SFDR performance and two-tone intermodulation distortion over a broad output bandwidth of 200 MHz. The first public demonstration of the DAC1627D will be made in the NXP booth (no. 420) at IMS2011, the IEEE MTT-S International Microwave Symposium held June 7-9, 2011 in Baltimore, Maryland.

Developed primarily for wireless infrastructure applications, the DAC1627D1G25 is fully compliant to the Multi-Carrier GSM spectral mask and the LTE and LTE-Advanced transmit specification, with comfortable margins. As a result, the DAC1627D is ideal for multi-standard radio base stations, allowing design engineers to employ a single DAC transmit architecture, which minimizes the system bill-of-material costs.
 
"The technology advances in cellular infrastructure demand ever higher performance in RF data converters. The introduction of NXP's DAC1627D, its high performance and high-speed digital to analog converter device, provides a compelling solution in this quickly evolving segment,” said Flint Pulskamp, wireless and wired communications semiconductor analyst at IDC.
 
"The achievement announced today, the highest performance RF DAC, is a culmination of decades of experience and innovation in high performance data converters,” said Maury Wood, general manager, High Speed Converters product line, NXP Semiconductors.“When combined with CGVxpress™ and CGV™, NXP’s implementation of the industry-leading JESD204A high speed serial interface, NXP has a roadmap that meets the most demanding digital radio transmitter signal fidelity requirements. NXP continues to work closely with our customers to bring new levels of radio frequency digital-to-analog performance to next-generation radio base stations, and other digital communications and signal synthesis applications."
 
The DAC1627D incorporates elements of NXP's CGV technology feature set, including Multi-Device Synchronization (MDS), which solves tough system synchronization and latency challenges in many digital communications system applications, including MIMO and active antenna array LTE radio base stations.
 
At IMS2011, NXP will also showcase the DAC1627D1G25 plus the BGX7100 IQ Modulator on a dedicated evaluation/demonstration printed circuit board which, in combination, deliver optimum RF performance.


Source

Sunday, February 27, 2011

Organic chips - not just in your kitchen anymore

silicon wafer

(PhysOrg.com) -- IMEC researchers at the International Solid-State Circuits Conference, in San Francisco, California are expected to introduce a microprocessor made with organic semiconductors.

This breakthrough, which will be a world's first, is going to have theof a chip from roughly the 1970's, with a 4000-transistor, 8-bit logic circuit. This is admittedly, not an amazing amount of power but this little chip, unlike its metal counterparts, is able to bend without breaking. So, while you may not be supercomputing with organic semiconductors anytime in the near future, these cheaper and more flexible chips could be used in a variety of flexible displays or to create sensors in areas where normal chips could never go.

Organic semiconductors do have one major difference from their silicon cousins. In athe chips have a monocrystalline structure that creates switches that act in a very predictable manner. When the voltage is above the known threshold the switch will turn on.

In the organic version of the transistors, silicon has been replaced by an unnamedthat is a bit more unpredictable, each chip will have a slightly different switching threshold. In display based applications, such as in e-readers, this does not notably effect the performance of the device, but in a single transistor this variance can keep the chip from working properly.

In order to solve this problem researchers built an extra gate into the back of each transistor on the 25-micrometer-thick chip. The chip is backed by an extremely thin polyethylene naphthalate, which is about the thickness of the plastic wrap found in the average kitchen. Currently creating the chip is about one tenth the cost of more traditional chips.


Source

Saturday, February 26, 2011

More news stories

Toyota's musical robots (w/ Video)

[Annonce]

(PhysOrg.com) -- The odds are that when you talk to the average person on the street they will have an opinion on what type of music is good and what type is bad. We tend to think of music as a human thing, ...

Electronics/Robotics

created1hour ago |popularity3.7/ 5 (3) |comments0 |with audio podcastweblog


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Friday, February 25, 2011

More News

ONR's TechSolutions creating green ideas that light up ships and submarines

Find more news articles via<a href="http://www.physorg.com/sort/date/all/">sort by date</a>page


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Thursday, February 24, 2011

Low power, programmable cell array demonstrated by NEC

Low power, programmable cell array demonstrated by NEC

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NEC Corporation announced today the successful demonstration of a low power programmable cell array using a rewritable and nonvolatile solid-electrolyte switch,"NanoBridge,"integrated into a 90nm CMOS.

NanoBridge is the resistive switch where resistance changes between ON and OFF states when a nanometer scale Cu bridge is precipitated or dissolved into the solid. When placed between the two Cuof LSI, NanoBridge can connect or disconnect the two interconnects by applying a bias voltage. Therefore,can be configured after manufacturing in order to implement logic functions. Each NanoBridge state is nonvolatile and it maintains its resistive state without power dissipation.

This new technology features a programmable switch equipped with NanoBridge that is monolithically stacked on programmable logic circuits composed of transistors. Theof NanoBridge, such as the distribution of turn-on voltage, have been improved by introducing a newly developed PSE (polymer solid-electrolyte). These technologies have reduced chip size by 1/4 and reduced dynamic power consumption by 1/4 when compared to a reference programmable array using SRAM (static) based switches.

These latest NanoBridge developments feature the following:

The programmable switch plane is monolithically stacked on the logic plane, which results in a 1/4 chip size reduction and a 1/4 reduction in dynamic power consumption when compared with conventional technology.
The switch plane is composed of NanoBridges that configure LSI interconnects and NanoBridges that configure the logic circuit. The logic plane features newly developed programmable logic from NEC that has the same functionality as conventional programmable logic even though it is smaller in size. This is due to the substantial number of NanoBridges in the switch plane. As a result, both the chip size and dynamic power have been reduced by 1/4 when compared to the conventional programmable array with SRAM-based switches.

The distribution of NanoBridge electrical properties has been improved by introducing a newly developed solid-electrolyte, PSE.
The uniform formation of aCu bridge results in a more narrow distribution of turn-on voltage. This leads to the successful programming of a 32x32 crossbar switch without select transistors in the logic plane, which eliminates the need for additional area due to NanoBridges in the logic plane.

Currently, cloud computing is becoming increasingly widespread, and a larger number of transactions are being processed by computer and communications tools. As a result, managing the power of these instruments has become a serious challenge, where it is necessary to preserve the quality of computing while decreasing the power consumption of Si chips.

Transactions processed by a CPU (central processing unit) require more power and computing time than transactions processed by hardware such as an accelerator chip, which is specialized for processing specific transactions.

This innovative low power programmable array helps to reduce the power consumption of instruments by processing different kinds of transactions through the reconfiguration of circuits, which enables lower power consumption and shorter computing times.

These newly developed technologies are a result of NEC's long-time development of NanoBridge technology, which enabled the first time successful operation of low power programmable cell arrays. Looking forward, NEC will continue to promote the development of innovative new programmable devices.

NEC will present these NanoBridge based programmable cell array achievements at the International Solid-State Circuit Conference (ISSCC) held in San Francisco from February 20, 2011. NEC will present NanoBridge technologies on February 22.


Source

Tuesday, February 22, 2011

New energy-saving flip-flop circuit developed by Toshiba

New energy-saving flip-flop circuit developed by Toshiba

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Toshiba Corporation today announced that it has developed a new flip-flop circuit using 40nm CMOS process that will reduce power consumption in mobile equipment. Measured data verifies that the power dissipation of the new flip-flop is up to 77% less than that of a typical conventional flip-flop and that it achieves a 24% reduction in total power consumption when applied to a wireless LAN chip.

A flip-flop is a circuit that temporarily stores one bit of data during arithmetic processing by a digital system-on-a-chip (SoC) incorporated in mobile equipment and other digital equipment. As a typical SoC uses 100,000 to 10 million flip-flops they are an essential part of an SoC design.

New energy-saving flip-flop circuit developed by Toshiba
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Circuit configuration of new technique.

A typical flip-flop incorporates a clock buffer to produce a clock inverted signal required for the circuit's operation. When triggered by a signal from the clock, the clock buffer consumes power, even when the data is unchanged. In order to reduce this power dissipation, a power-saving design technique called clock gating is widely used to cut delivery of the clock signal to unused blocks. However, after applying the clock gating, the flip-flop active rate, a measure of data change rate per clock, is only 5-15%, indicating that there is still plenty of room for further power reduction.

In order to save power, Toshiba changed the structure of the typical flip-flop and eliminated the power-consuming clock buffer. This approach brings with it the problem of data collision between the data writingand the state holding circuitry in the flip-flop, which Toshiba overcame by adding adaptive coupling circuitry to the flip-flop. A combination of an nMOS transistor and a pMOS transistor, this circuitry adaptively weakens state-retention coupling and prevents collisions. Despite the addition of the adaptive coupling circuitry, overall simplification of the basic flip-flop configuration reduces the transistor count from 24 to 22, and the cell area is less than that of the conventional flip-flop.

This achievement will be announced on February 23 (local time) at the 2011 IEEE International Solid-State Circuits Conference (ISSCC) now being held in the United States.


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Saturday, February 19, 2011

Intel ships world's smallest HSPA+ solution for 3G smart phones

Intel Mobile Communications today announced shipment of its XMM 6260 platform to key customers. Optimized for smart phone architectures coupled with an application processor or as a standalone solution for PC modems and data cards, the advanced HSPA+ platform is based on the X-GOLD 626 baseband processor and the SMARTi UE2 RF transceiver. Combined with the 3GPP Release 7 protocol stack, the XMM 6260 platform comprises a fully integrated HSPA+ system solution supporting HSPA category 14 (21Mbps) in the downlink and category 7 (11.5Mbps) in the uplink.

"With shipping of the XMM 6260 platform ahead of schedule we continue the fast evolution of our leading baseband and transceiver technology by adding advanced+ features,"said Prof. Dr. Hermann Eul, president of Intel Mobile Communications."The fourth generation of successful 3G platforms underlines our technology leadership and our customers benefit from lower cost and space savings, which significantly increase design flexibility to create unique and feature-rich handsets and mobile Internet cards with innovative form factors."

The XMM 6260 platform is based on the X-GOLD 626 baseband processor, manufactured by TSMC in leading-edge 40nm process technology. The X-GOLD 626 integrates a power management unit, enabling world-classin both active and idle mode. The processor is combined with the SMARTi UE2 RF transceiver. Leveraging from a power-saving 65nm CMOS technology the transceiver uses a unique digital architecture that significantly reduces the number of power amplifiers and RF components, resulting in reduced board space and power consumption. The XMM 6260 smart phone modem platform enables HSPA+ designs in less than 600mm2 PCB (Printed Circuit Board) area, making them among the smallest comparable solutions worldwide.

The common and scalable ARM11-based processor architecture used across all 2G and 3G platforms ensures Intel Mobile Communications customers a high degree of reuse of their hardware and software investment when developing handsets across the entire cellular portfolio. In addition, theincludes numerous advanced 3GPP Release 7 features such as receive diversity, interference cancellation and CPC (Continuous Packet Connectivity) that significantly improve power consumption and system performance.

The XMM 6260 is available in volume and will be presented at the Intelbooth (Hall 1, Booth B22) during the Mobile World Congress in Barcelona from Feb. 14-17. Worldwide shipment to key customers has already started and design-in of the XMM 6260 is supported by a complete reference design.


Source

Friday, February 18, 2011

Elpida to buy Powerchip's DRAM operations: report

Japan's leading chip maker Elpida Memory will take over the DRAM operations of Taiwan's Powerchip Technology in a bid to increase competitiveness amid falling prices, the Nikkei said Monday.

Powerchip will end production of its own DRAM chips, used in personal computers, and will focus exclusively on production for Elpida, which plans to eventually acquire Powerchip's main production facilities, the daily said.

Falling prices ofhas accelerated the talks between the two partners, who plan to finish the negotiations by the end of March, the Nikkei said.

Elpida had a 17.4-percent share of the global DRAM market in 2009, while Powerchip held 2.1 percent, the Nikkei said.

Samsung led the market with a 33.6 percent share, followed by South Korean rival Hynix Semiconductor with 21.6 percent, the Nikkei said.

The global DRAM market came to around four trillion yen (48.7 billion dollars) in 2010, with products for PCs accounting for 80-90 percent, the Nikkei said.


Source

Thursday, February 17, 2011

National Semiconductor demonstrates 28 gbps data center technology

National Semiconductor Corp. today announced it has achieved a breakthrough in high-speed signal conditioning by becoming the first company to successfully demonstrate 28 Gbps discrete quad-channel retimer technology with ultra-low power consumption to drive 100 Gbps to 400 Gbps interfaces in next-generation data center systems.

"Rapidly increasing Global IP traffic is fueling the need for higher bandwidth interconnect solutions capable of driving high-speed signals and consuming low power overor,"said Linley Group Senior Analyst Jag Bolaria."Asincrease from 10 Gbps to 100 Gbps, signal integrity requirements become more stringent forin chip-to-chip, chip-to-module, and backplane applications.is addressing this need with long reach, low power retimer technology that includes proven signal integrity.”

National will demonstrate this breakthrough 28 Gbps retimer technology in its partner booths at DesignCon 2011 being held Jan. 31– Feb. 3 at the Santa Clara Convention Center. National’s demonstration, in Molex Booth and Amphenol Booth, will use a real-world backplane and cable setup to highlight the retimer's clean output eye, zero bit errors and superior jitter performance essential to enabling 100 Gbps to 400 Gbps interconnects.

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Nate and Jitendra preview National's 25 - 28 Gbps retimer technology.

“Next-generation data center systems require an ecosystem of ASICs, interconnects and interface ICs to support the 100 Gbps data rate,” said Greg Walz, group product manager for the Integrated Products Division at Molex."National Semiconductor retimer ICs combined with Molex interconnects will enable system vendors to achieve ultra-high performance 100 Gbps pluggable I/O and backplane solutions for Ethernet and InfiniBand applications."

National’s third-generation silicon-germanium (SiGe) BiCMOS process and ground-breaking analog technology enables 28 Gbps data path retimers for chip-to-optics, chip-to-backplane, and chip-to-chip interfaces. The SiGe BiCMOS process produces high bandwidth and low noise transistors that enable low jitter and ultra-low power in high speed analog signal conditioning circuits. These advantages are also built into National’s recently announced family of 10 Gbps repeaters, which includes the quad-channel DS100BR410, dual-channel unidirectional DS100BR210 and single-lane bidirectional DS100BR111.


Source

Tuesday, February 15, 2011

Saving greenhouse power with deep-red LED light

Saving greenhouse power with LED light

The Siemens subsidiary Osram Opto Semiconductors has developed a powerful light-emitting diode (LED) for use in the cultivation of plants. It emits a deep-red light at a wavelength of 660 nanometers, which is perfect for plant photosynthesis. With an efficiency of 37 percent— one of the highest for a light source of this color— it also yields considerable energy savings compared to conventional lamps. In a pilot project in Denmark, which used around 50,000 LEDs to illuminate a cultivation area of several thousand square meters, power consumption in the greenhouse fell by 40 percent.

Relatively little of the light used by plants for their growth is from the visible light spectrum. Chlorophyll molecules mostly absorb deep-red and blue light for the purposes of photosynthesis. Osram Opto Semiconductors has therefore developed an extremely efficient redwith an emission curve that is very closely matched to the spectral sensitivity of chlorophyll. The new LED is based on the thin-film technology used for high power semiconductor chips.

In greenhouse cultivation, some plants are grown on several levels stacked on top of one another. For this reason, the new LED is available in two variants, each with a different beam angle. The Golden Dragon Plus has a beam angle of 170 degrees and is therefore well suited for use in reflector lamps for illuminating large areas under cultivation. By contrast, the Oslon SSL LED, with a beam angle of 80 degrees, is designed for use in multi-level applications, such as those for the cultivation of lettuce. Using LED light, it is also possible to promote different growth phases of the plant under. Red light, for example, encourages plants to grow in length, whereas blue light fosters bud formation, for example. Controlled variation of the proportion of blue light between ten and 30 percent reduces use of fertilizer and other chemicals.

Compared to conventional high-pressure sodium lamps, the luminous efficacy of the system as a whole is 60 percent higher with red and blue LEDs. And with a service life of 100,000 hours, the LEDs provide maintenance-free operation for many years. Also involved in the pilot project with Osram were Arrow Electronics and Fiona Lighting A/S, a Danish company specializing in LED lighting for commercial horticulture. Highly efficient LED lighting forms part of theenvironmental portfolio, which generated around€28 billion in sales for the company in fiscal year 2010.


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Saturday, February 12, 2011

Researchers develop a full numerical model of EUV imaging and exposure statistics

The tolerances on feature size, shape, and placement for next generation computer chips fabricated with extreme ultra-violet (EUV) lithography will range from a maximum of a few nanometers down to less than 1 nm.

To achieve these tolerances, the sidewallof the features, traditionally called line edge roughness (LER), is required to be less than 2 nm.

The CNST’s Gregg Gallatin and Lawrence Berkley National Laboratory’s Patrick Naulleau have developed a numerical model* that accounts for the two dominant sources of LER: the quantum statistics of exposing and developing the resist; and the roughness of the mask features themselves.

Mask LER is about 10 nm, which reduces to 2 nm on theusing a 5X EUV imaging system.

The model determines the relative contribution each LER source makes to the wafer under various imaging and processing conditions. It predicts wafer LER and also determines to what extent the frequency content of the mask contribution is altered by the imaging, exposure, and development processes.

The researchers have discovered that there are combinations of processes where the mask induced roughness is the dominant contributor to wafer LER, but its frequency signature is virtually indistinguishable from the contributions of exposure and development statistics alone.

Therefore, other direct metrology methods in addition to wafer LER frequency content will be required to determine the separate contributions. This work supports the continued progress of semiconductor manufacturing technology.


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Friday, February 11, 2011

New transistor for plastic electronics exhibits the best of both worlds

New transistor for plastic electronics exhibits the best of both worlds

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Researchers at Georgia Tech have developed a transistor with excellent stability and performance for use on plastic electronics. In addition, it can be manufactured at relatively low temperatures in a regular atmosphere.

In the quest to develop flexible, one of the stumbling blocks has been creatingwith enough stability for them to function in a variety of environments while still maintaining the current needed to power the devices. Online in the journal, researchers from the Georgia Institute of Technology describe a new method of combining top-gate organic field-effect transistors with a bilayer gate insulator. This allows the transistor to perform with incredible stability while exhibiting good current performance. In addition, the transistor can be mass produced in a regular atmosphere and can be created using lower temperatures, making it compatible with the plastic devices it will power.

The research team used an existingand changed thebecause transistor performance depends not only on the semiconductor itself, but also on the interface between the semiconductor and the gate dielectric.

"Rather than using a single dielectric material, as many have done in the past, we developed a bilayer gate dielectric,"said Bernard Kippelen, director of the Center for Organicand Electronics and professor in Georgia Tech's School of Electrical and Computer Engineering.

The bilayer dielectric is made of a fluorinatedknown as CYTOP and a high-k metal-oxide layer created by. Used alone, each substance has its benefits and its drawbacks.

CYTOP is known to form few defects at the interface of the organic semiconductor, but it also has a very low dielectric constant, which requires an increase in drive voltage. The high-k metal-oxide uses low voltage, but doesn't have good stability because of a high number of defects on the interface.

So, Kippelen and his team wondered what would happen if they combined the two substances in a bilayer. Would the drawbacks cancel each other out?

"When we started to do the test experiments, the results were stunning. We were expecting good stability, but not to the point of having no degradation in mobility for more than a year,"said Kippelen.

The team performed a battery of tests to see just how stable the bilayer was. They cycled the transistors 20,000 times. There was no degradation. They tested it under a continuous biostress where they ran the highest possible current through it. There was no degradation. They even stuck it in a plasma chamber for five minutes. There was still no degradation.

The only time they saw any degradation was when they dropped it into acetone for an hour. There was some degradation, but the transistor was still operational.

No one was more surprised than Kippelen.

"I had always questioned the concept of having air-stable field-effect transistors, because I thought you would always have to combine the transistors with some barrier coating to protect them from oxygen and moisture. We've proven ourselves wrong through this work,"said Kippelen.

"By having the bilayer gatewe have two different degradation mechanisms that happen at the same time, but the effects are such that they compenstate for one another,"explains Kippelen."So if you use one it leads to a decrease of the current, if you use the other it leads to a shift of the thereshold voltage and over time to an increase of the current. But if you combine them, their effects cancel out."

"This is an elegant way of solving the problem. So, rather than trying to remove an effect, we took two processes that compliment one another and as a result you have a result that's rock stable."

The transistor conducts current and runs at a voltage comparable to amorphous silicon, the current industry standard used on glass substrates, but can be manufactured at temperatures below 150°C, in line with the capabilities of plastic substrates. It can also be created in a regular atmosphere, making it easier to fabricate than other transistors.

Applications for these transistors include smart bandages, RFID tags, plastic solar cells, light emitters for smart cards– virtually any application where stable power and a flexible surface are needed.

In this paper the tests were performed on glass substrates. Next, the team plans on demonstrating the transistors on flexible plastic substrates. Then they will test the ability to manufacture the bilayer transistors with ink jet printing technologies.


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Thursday, February 10, 2011

Industry benchmark results tripled with Qorivva microcontrollers

Freescale Semiconductor announced today that one of its Power Architecture based Qorivva microcontrollers (MCUs) reached unprecedented levels of performance in an industry-standard automotive benchmark test. The Qorivva 32-bit MPC5674F achieved a benchmark score of 305 Automarks in the Embedded Microprocessor Benchmark Consortium’s AutoBench suite of tests, demonstrating more than three times the performance of the previous highest score set by a competitor. Additionally, Freescale’s MPC564xA and MPC5566 MCUs scored 150 and 121 Automarks, respectively.

The benchmark assesses an MCU’s performance by first performing a set of typical automotive processes, such as controller area network, tooth-to-spark (locating the engine’s cog when the spark is ignited) and road speed calculation, and then adding complex signal processing algorithms used in engine control or vehicle safety applications. The benchmark is used to help automotive engineers assess relative performance between embedded MCUs for automotive applications.

“Confirming such outstanding performance by our Qorivva MCUs is great news,” said Ray Cornyn, director of Freescale’s Automotive MCU business.“Developed from the original Power Architecture technology, we have been enhancing and focusing the Qorivva Architecture to provide exceptional real time embedded processing capabilities and the excellent results shown from these latest implementations illustrates why Power Architecture technology remains the automotive market standard.”

The performance of the MPC5674F, which was designed specifically for electronic engine control, enables automotive engineering teams to bring cost-effective, clean-engine technology to the broad market for today’s combustion engines. Due to its extensive computing power and advanced motor control capability, the MPC5674F can also power the next generation of hybrid and electric vehicles. The computing capability of the engine controller enables precision electronic control of today’s direct injection fuel systems, which typically saves 10-20 percent in fuel consumption over traditional systems, according to the US Dept. of Energy. In terms of global fuel consumption, the savings from electronic control has the potential to reach 100 million gallons of fuel per year.

Direct injection fuel systems need a high level of computing performance to precisely control when to inject fuel and the duration that the injector remains open, while simultaneously monitoring multiple external events such as oxygen levels, air temperature, road speed and exhaust gas composition in order to optimize the delivery of fuel for clean burning and optimal engine efficiency.

The Qorivva MPC5674F MCU is designed to run at higher central processing unit frequencies compared to early engine computers. This means it can execute individual tasks faster than other comparable devices. It is also engineered to run several processes in parallel, so it can execute dual instructions and compute complex signal processing algorithms simultaneously. This gives automotive developers a unique performance opportunity with which to optimize today’s combustion engines as well as hybrids and electric vehicles. This performance is delivered within the framework of Freescale’s zero-defect design and manufacturing process, which enables auto makers to offer extensive powertrain warranties.

The next generation of Qorivva MCUs, based on Power Architecture® technology, is built using an advanced 55 nanometer (nm) non-volatile memory (NVM) process for improved power efficiency and cost effectiveness and features an innovative, multicore architecture. Qorivva MCUs include leading-edge integration and performance capabilities, including configurable peripheral sets such as flexible timers and motor control systems. Digital signal processing capabilities provide additional functionality. With these features, Qorivva MCUs provide the freedom to architect the ideal solution for a particular application.

The Qorivva MPC5674F is currently sampling and is expected to be auto qualified in mid-2011.


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Wednesday, February 9, 2011

Texas Instruments announced the OMAP 5 chipset with gesture-based support

(PhysOrg.com) -- Texas Instruments is bringing a new chipset to the market, with the potential to support gesture-based interfaces and possibly Microsoft's ARM-based version of Windows. The new chipset is called the OMAP 5 mobile platform. The system's chip will work with what is expected to have a gesture-based system similar to Microsoft's current video game hardware, Kinect.

The OMAP 5is based on the brand-new ARM Cortex-A15 processor, which allows for more than 4GB of memory and support for multiple operating systems when virtualized in the hardware. This type of setup could allow for a mobile device that is Android-based in your hand, and Windows-based when you plug it into a dock and use it as your computer.

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A similar setup was shown in the product demo video. This scenario is in-line with the list of operating systems thatexecutives expect to target for future devices. This list includes: Android, Chrome OS, andWindows. While running multiple operating systems is possible now, Texas Instruments expects that this combination will allow for the running of multiple operating systems much more easily.

The chipset will be paired with a multi-core Imagination PowerVR SGX544 GPU processor. The company expects that this combination will have five times the graphics performance of the current SGX540 model. The Imagination PowerVR SGX544 GPU also has support for Microsoft's DirectX 9.

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The chip is expected to be released later this year, though consumer devices featuring the chip will most likely not be on sale until 2012. No details about devices that the chips may end up in has been released at this time.


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Saturday, February 5, 2011

World's first process technology for copper-internal-electrode-based capacitors for high-Speed LSIs developed

World's first process technology for copper-internal-electrode-based capacitors developed

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Fujitsu Laboratories today announced the development of a process technology to produce capacitors for high-speed LSI chips, which as a world's first employs copper for internal electrodes. The use of copper for internal electrodes lowers the impedance of the capacitor itself, and by mounting the capacitor directly below the LSI chip, impedance from the circuits can also be reduced, resulting in increase of current-flow efficiency by 10 times compared to previously available technology. The new technology is expected to enable the next generation of high-speed computers to operate at even higher speeds.

As LSI chips continue to achieve higher speeds and higher integration densities, and with many of a chip's elements all operating simultaneously, much of the current used by theis consumed in bursts. This can lower voltages, which may impact proper operation. In those instances in which much current is consumed, it is desirable to mount anear the LSI chip to instantly supplement the current.

Conventionally, ceramic-chip condensers being used as power-supply capacitors have been mounted on the surface or rear of the circuit board or LSI chip package, supplying current to the LSI chip through the circuit wires. This method results in a relatively long electrical pathway between the capacitor and LSI chip, which raises impedance and would potentially create instabilities in future high-speed computers. In addition, because nickel, which has comparatively high resistance, has conventionally been used for the internalin the capacitor, the impedance of the capacitor itself has been high, limiting the speed of the power-supply current.

Fujitsu Laboratories developed a basic manufacturing method for capacitors that can provide high-speed, stable supply of current to an LSI chip.

The production of capacitors with the following key characteristics has been made possible using nano-particle deposition technology:

1. Internal electrodes made using low-resistance copper (a world's first)
2. Ultra-fine through-hole contact construction enabling connection directly beneath the LSI chip
3. High-reliability thin-film dielectric layer enabling high capacitance (1µF/cm2·layer)

Employing copper for the internal electrodes to lower the impedance of the capacitor itself reduces the length of the circuits between the capacitor and the LSI chip, making it is possible to limit impedance of the power-supply line. These factors together result in a power supply that is 10 times as efficient for operationally stable high-speed LSI chips, a development that is expected to contribute to higher computer speeds.

World's first process technology for copper-internal-electrode-based capacitors developed
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Manufacturing process for Fujitsu's newly-developed capacitor.

Laboratories will continue with development of technologies to enable miniaturization of the capacitor terminals and multi-layering, aiming to apply this new technology to computers around 2015.


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Friday, February 4, 2011

6MHz buck-boost DCDC convertor IC allows for smaller external components, wider battery voltage range

Smaller external components, wider battery voltage range in new convertor

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Fujitsu Semiconductor Limited today announced the development of 6MHz buck-boost DCDC convertor IC"MB39C326"for radio frequency power amplifiers in mobile phones, smart phones, e-books and other handheld mobile devices. Sample shipments for the new IC product, MB39C306, will start from June 2011.

“MB39C326” operates at an industry-leading 6MHz as the buck-boost DCDC converter IC for radio frequency power amplifiers. The higher frequency operation of 6MHz can largely reduce the mounting area of the power supply part (half the ratio of existing products.)

Buck-boost operation makes it possible for Li-ionto operate at wider battery voltage range.“MB39C326” makes it possible to deliver stable voltages for the equipment and extend the life of Li-ion batteries, when the voltage of Li-ion batteries drops.

Mobile phones,, e-book and other handheld mobile devices are demanding higher performance with larger data transfer capacity, while aggressively miniaturizing components and board space. There is a strong push to reduce the overall size of RF amplifier without sacrificing stability and efficiency of its power supply. The passive inductor is one of the larger components requiring large space. With DCDC convertors switching at higher frequencies, inductor size can be reduced. Fujitsu Semiconductor’s DCDC convertor switches at 6MHz compared to conventional 2 to 3MHz, allowing a smaller inductor to be used and can be expected to reduce the overall board space of the power management circuits by half. Its buck boost operation switches automatically to extend the operating voltage of the lithium battery, while providing stableto the power amplifier.

Semiconductor will introduce the new buck-boost DCDC convertor, MB39C326, at the Mobile World Congress in Barcelona from 14th to 17th February 2011. Samples will be available in June 2011.


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Thursday, February 3, 2011

New technique boosts high-power potential for gallium nitride electronics

New technique boosts high-power potential for gallium nitride electronics

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Gallium nitride (GaN) material holds promise for emerging high-power devices that are more energy efficient than existing technologies– but these GaN devices traditionally break down when exposed to high voltages. Now researchers at North Carolina State University have solved the problem, introducing a buffer that allows the GaN devices to handle 10 times greater power.

"For future renewable technologies, such as the smart grid or electric cars, we need high-power semiconductor devices,"says Merve Ozbek, a Ph.D. student at NC State and author of a paper describing the research."And power-handling capacity is important for the development of those devices."

Previous research into developing high power GaN devices ran into obstacles, because large electric fields were created at specific points on the devices' edge when high voltages were applied– effectively destroying the devices. NC State researchers have addressed the problem by implanting a buffer made of the element argon at the edges of GaN devices. The buffer spreads out the electric field, allowing the device to handle much higher voltages.

The researchers tested the new technique on Schottky diodes– common electronic components– and found that the argon implant allowed the GaN diodes to handle almost seven times higher voltages. The diodes that did not have the argon implant broke down when exposed to approximately 250 volts. The diodes with the argon implant could handle up to 1,650 volts before breaking down.

"By improving the breakdown voltage from 250 volts to 1,650 volts, we can reduce the electrical resistance of these devices a hundredfold,"says Dr. Jay Baliga, Distinguished University Professor of Electrical and Computer Engineering at NC State and co-author of the paper."That reduction in resistance means that these devices can handle ten times as much power."


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Wednesday, February 2, 2011

A matter of timing: New strategies for debugging electronics

(PhysOrg.com) -- The components that make up the integrated circuits in electronic devices are nano-sized and number in the billions. Sometimes"bugs"lurking in these complex systems can emerge and cause significant performance errors.

One category of electronic bugs that can occur after a chip is fabricated is known as timing errors. These errors can cause components to slow down and take longer to execute operations. As components continue to become smaller, the process of preventing and solving timing errors is becoming ever more complex, increasing the time it takes to send new products to market.

University of Wisconsin-Madison Electrical and Computer Engineering assistant professor Azadeh Davoodi is one of the first people to look at solutions for timing errors, and she has received a 2011 Faculty Early Career Development Award (CAREER) and grant to support her work.

Sponsored by the National Science Foundation, CAREER awards recognize faculty members who are at the beginning of their academic careers and have developed creative projects that effectively integrate advanced research and education.

go through a rigorous testing process to find and correct bugs that can cause performance errors. However, the small size and sheer volume of components mean chips realistically cannot be entirely validated before fabrication.

"These errors occur, not because the circuit isn't functioning correctly, but because it fails to operate correctly at the desired speed,"Davoodi says."The nanoscale components in the chip are so small they can have weird physical behaviors that can only be detected after they are fabricated."

The validation process involves manually opening up a chip and examining billions of, which is extremely time-consuming. Timing errors often are interdependent, meaning they emerge only when certain operations are performed together. This means testing for timing errors requires predicting the chip's behavior during a vast number of possible operations and combinations of operations.

It can several months to find errors and alter chips during the validation process. Most of this time is spent dealing with timing errors, so while timing errors are not the most common problems, they are a significant factor in delaying the time to market of new chips.

Davoodi's team will develop special sensor components that can be added to a chip's design, as well as methods to analyze measurements from the components. The new components will provide custom timing information for a particular chip design, allowing developers to predict, detect and even solve errors more quickly.

Instead of manually opening up and examining chips, developers could simply use data from the sensor components as a compact representation of important areas of the design that may be causing timing errors.

"We want to increase the timing observability inside the chip,"Davoodi says.

In addition to supporting cutting-edge research, CAREER awards also fund innovative outreach programs. Along with developing technical coursework to introduce undergraduate students to sophisticated software programming, Davoodi is creating a unique course module that looks at some of the non-technical aspects of computer engineering that could inspire students to pursue the field.

The course module will be part of an introductory engineering course called Introduction to Society's Engineering Grand Challenges and explore the One Laptop Per Child project. The module will look at the societal, ethical and political implications of disseminating and using technology in developing countries.

"These aspects of the case study can be used as a different angle to interest students, particularly women, to get excited about engineering,"Davoodi says.


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Friday, January 21, 2011

New device may revolutionize computer memory

(PhysOrg.com) -- Researchers from North Carolina State University have developed a new device that represents a significant advance for computer memory, making large-scale"server farms"more energy efficient and allowing computers to start more quickly.

Traditionally, there are two types of computer memory devices. Slow memory devices are used in persistent data storage technologies such as flash drives. They allow us to save information for extended periods of time, and are therefore called nonvolatile devices. Fast memory devices allow our computers to operate quickly, but aren’t able to save data when the computers are turned off. The necessity for a constant source of power makes them volatile devices.

But now a research team from NC State has developed a single“unified” device that can perform both volatile and nonvolatile memory operation and may be used in the main memory.

“We’ve invented a new device that may revolutionize,” says Dr. Paul Franzon, a professor of electrical and computer engineering at NC State and co-author of a paper describing the research.“Our device is called a double floating-gate field effect transistor (FET). Existing nonvolatile memory used indevices utilizes a single floating gate, which stores charge in the floating gate to signify a 1 or 0 in the device– or one‘bit’ of information. By using two floating gates, the device can store a bit in a nonvolatile mode, and/or it can store a bit in a fast, volatile mode– like the normal main memory on your computer.”

The double floating-gate FET could have a significant impact on a number of computer problems. For example, it would allow computers to start immediately, because the computer wouldn’t have to retrieve start-up data from its hard drive– the data could be stored in its main memory.

The new device would also allow“power proportional computing.” For example, Web server farms, such as those used by Google, consume an enormous amount of power– even when there are low levels of user activity– in part because the server farms can’t turn off the power without affecting their main memory.

“The double floating-gate FET would help solve this problem,” Franzon says,“because data could be stored quickly in– and retrieved just as quickly. This would allow portions of the server memory to be turned off during periods of low use without affecting performance.”

Franzon also notes that the research team has investigated questions about this technology’s reliability, and that they think the device“can have a very long lifetime, when it comes to storing data in the volatile mode.”


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Friday, January 14, 2011

IBM and Samsung collaborate on chip research

US computer giant IBM has teamed up with South Korean electronics titan Samsung to improve their chip technology

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US computer giant IBM and South Korean electronics titan Samsung have announced they will begin working together on ways to make better chips for smartphones and other gadgets.

Samsung researchers will team with scientists at the IBM Semiconductor Research Alliance in New York State to create"solutions that are optimized for performance, power consumption, and size."

"Collaborative innovation will be critical if the semiconductor industry is to continue driving new forms ofand new methods of computing,"said IBM microelectronics general manager Michael Cadigan.

"That's why we're excited to havescientists working with us at the most fundamental stages of the R&D process."

The companies are striving to develop chips to power a high-performance generation of"smarter, connected and more mobile"devices.


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Friday, January 7, 2011

Using 30nm class technology, Samsung develops industry's first DDR4DRAM

Using 30nm class technology, Samsung develops industry's first DDR4DRAM

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Samsung Electronics announced today that it completed development of the industry’s first DDR4 DRAMmodule last month, using 30 nanometer (nm) class process technology.

“Samsung has been actively supporting the IT industry with our greeninitiative bycoming up with eco-friendly, innovative memory products providing higher performance and power efficiency every year,” said Dong Soo Jun, president, memory division,.“The new DDR4 DRAM will build even greater confidence in our cutting-edgegreenmemory, particularly when we introduce four-gigabit (Gb) DDR4-based products using next generationfor mainstream application.”

The new DDR4 DRAM module can achieve data transfer rates of 2.133 gigabits per second (Gbps)at 1.2V, compared to 1.35V and 1.5V DDR3 DRAM at an equivalent 30nm-class process technology, with speeds of up to 1.6Gbps. When applied to a notebook, it reduces power consumption by 40 percent compared to a 1.5VDDR3 module.

The module makes use of Pseudo Open Drain (POD), a new technology that has been adapted to high-performance graphic DRAM to allow DDR4 DRAM to consume just half the electric current of DDR3 when readingand writing data.

By employing new circuit architecture, Samsung’s DDR4 will be able to run from 1.6 up to 3.2Gbps, compared to today’s typical speeds of 1.6Gbps for DDR3 and 800Mbps for DDR2.

Late last month, Samsung provided 1.2V 2gigabyte (2GB) DDR4 unbuffered dual in-line memory modules (UDIMM) to a controller maker for testing.

Samsung now plans to work closely with a number of server makers to help insure completion of JEDEC standardization of DDR4 technologies in the second half of this year.

Samsung has been leading the advancement of DRAM technology ever since it developed the industry’s first DDR DRAM in 1997. In 2001, it introduced the first DDR2 DRAM, and in 2005, announced the first DDR3using 80nm-class technology.


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Wednesday, January 5, 2011

Scientists squeeze more than 1,000 cores on to computer chip

(PhysOrg.com) -- Scientists at the University of Glasgow have created an ultra-fast 1,000-core computer processor.

Theis the part of a computer’s central processing unit (CPU) which reads and executes instructions. Originally, computers were developed with only one corebut, today, processors with two, four or even sixteen cores are commonplace.

However, Dr Wim Vanderbauwhede and colleagues at the University of Massachusetts Lowell have created a processor which effectively contains more than a thousand cores on a single chip.

To do this, the scientists used a chip called a Field Programmable Gate Array (FPGA) which like all microchips contains millions of transistors– the tiny on-off switches which are the foundation of any electronic circuit.

FPGAs can be configured into specific circuits by the user, rather than their function being set at a factory, which enabled Dr Vanderbauwhede to divide up the transistors within the chip into small groups and ask each to perform a different task.

By creating more than 1,000 mini-circuits within the FPGA chip, the researchers effectively turned the chip into a 1,000-core processor– each core working on its own instructions.

The researchers then used theto process an algorithm which is central to the MPEG movie format– used in YouTube videos– at a speed of five gigabytes per second: around 20 times faster than current top-end desktop computers.

Dr Vanderbauwhede said:“FPGAs are not used within standard computers because they are fairly difficult to program, but their processing power is huge while their energy consumption is very small because they are so much quicker– so they are also a greener option.”

While most computers sold today now contain more than one processing core, which allows them to carry out different processes simultaneously, traditional multi-core processors must share access to one memory source, which slows the system down.

The scientists in this research were able to make the processor faster by giving each core a certain amount of dedicated memory.

Dr Vanderbauwhede, who hopes to present his research at the International Symposium on Applied Reconfigurable Computing in March 2011, added:“This is very early proof-of-concept work where we’re trying to demonstrate a convenient way to program FPGAs so that their potential to provide very fast processing power could be used much more widely in future computing and electronics.

“While many existing technologies currently make use of FPGAs, including plasma and LCD televisions and computer network routers, their use in standard desk-top computers is limited.

“However, we are already seeing some microchips which combine traditional CPUs withchips being announced by developers, including Intel and ARM.

I believe these kinds of processors will only become more common and help to speed up computers even further over the next few years.”


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